The present invention relates to the test and measurement of serial digital information, such as in a serial data communications system, and more particularly to a flexible timebase for EYE diagrams.
The uses of EYE diagrams to evaluate serial data communications systems, especially ones with an embedded clock, are well established. Many modern test instruments, such as oscilloscopes and waveform monitors, use EYE diagrams. There are several ways in use to generate the timebase for the EYE diagram.
1) Oscilloscopes traditionally use a direct trigger timebase.
2) A little used method has a free running timebase that is manually tuned to match the timebase of the incoming serial data.
3) Another method uses a phase-locked loop (PLL) derived timebase. The PLL derived timebase is sometimes preferred because it mimics the action of a clock recovery circuit to some degree. This allows a user to see jitter in the serial data stream timebase that may cause problems in data recovery, which problems are hidden by the direct trigger method. The PLL derived timebase may hide problems that are of less concern, but which are emphasized in the manually tuned method. If the loop bandwidth of the PLL is tunable, this allows the user to see or hide various elements of the jitter. As an extra benefit the PLL may be used to supply a “jitter demodulation” or “jitter demod” function where the jitter in the incoming serial data stream may be visualized as an edge-deflection or jitter versus time graph. The jitter demod function is very useful in identifying deterministic sources of jitter.
There are a few problems with the PLL derived timebase method. To be useful as a jitter evaluation tool the timebase of the measurement instrument has to be much better than the timebase of the incoming serial data. To get this degree of quality usually requires a stable timebase, but the requirement of a PLL is that the timebase be “pullable”, i.e., variable. In modern systems, such as television studio video delivery systems, there are several different data rates that add rate flexibility to the list of requirements. Such flexibility contradicts the basic timebase stability requirement. For an instrument that only has to deal with one data rate, such as 270 megabits per second, the timebase may be implemented as a phase-locked crystal. This works well, but there is a limit of about 10 KHz to loop bandwidth due to the crystal. To extend this to several data rate standards requires a separate crystal for each standard. To overcome this limitation direct digital synthesis of the timebase may be used. Although this is workable, the resulting analog design is somewhat complex and touchy.
With the advances being made in analog-to-digital converters and the decrease in price of digital processing, one may directly digitize the incoming serial data stream and recover the clock of the serial data stream via digital signal processing. A numerical controlled oscillator (NCO) may then be phase-locked to the recovered clock and used to derive the timebase for the EYE diagram. The quality of the timebase is dependent upon the quality of the sample clock for the analog-to-digital conversion, the quality of the analog-to-digital converter and the bit resolution carried through with the digital signal processing. However there is a problem when working with high data rates, such as the 1.5 gigabit per second high definition television rate, since the analog-to-digital converter required is quite expensive and the high quality, high frequency sampling clock is hard to achieve. The jitter performance of this method also is dependent to some degree on the record length of the serial data. Very long record lengths at high data rates are expensive.
Equivalent time sampling of a serial data signal for EYE diagrams using a high bandwidth sampler and a low frequency analog-to-digital converter (ADC) is known. However the difficulty is in deriving a stable, accurate timebase to achieve this. The sampling needs to be at twice the bandwidth of the jitter sidebands, which is set by the bandwidth of the clock recovery circuit.
What is desired is a method of combining the stability of a free running timebase with the advantages of a PLL timebase without using expensive analog-to-digital converters or hard to achieve high frequency sampling clocks while still maintaining the ability to evaluate timebase jitter.